-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 Format: 3.0 (native) Source: intel-microcode Binary: intel-microcode Architecture: i386 amd64 x32 Version: 3.20151106.1 Maintainer: Henrique de Moraes Holschuh <[email protected]> Uploaders: Giacomo Catenazzi <[email protected]> Homepage: http://feeds.downloadcenter.intel.com/rss/?p=483&lang=eng Standards-Version: 3.9.6 Vcs-Browser: http://git.debian.org/?p=users/hmh/intel-microcode.git Vcs-Git: git://git.debian.org/users/hmh/intel-microcode.git Build-Depends: debhelper (>= 7), iucode-tool (>= 0.9) Package-List: intel-microcode deb non-free/admin standard arch=i386,amd64,x32 Checksums-Sha1: 8c8a7ba10190b0b8e9f8a4c3ecf7b79615d03f08 977788 intel-microcode_3.20151106.1.tar.xz Checksums-Sha256: 04a15ad7d0234d47b303820913ab5889b64d95e40f95ec1ce2f86814680984ff 977788 intel-microcode_3.20151106.1.tar.xz Files: efce0b8f5dc73efc9722020313583954 977788 intel-microcode_3.20151106.1.tar.xz Autobuild: yes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBCgAGBQJWQUX+AAoJEJE3+9PebwqTfMUP/isAMMCufUE/QmFqeaTyV2tz +C2ePHl8lba9UQXdudLMKna//yHD+CyNgJwHC028NQIs+9R9G/MgQ0Mx6yiz9XVa p+RDufgepSS6SNKsju3mH17rsfZMZUmUVy2lPYoDNXWREts9xZOCqejMb350qnAc 6g43jhP4Z+T5yE2M1bbUVqxe960l3dV/EREgFEq0Jq7CWZhlJcfq0TneyzVPOuOd fVS56t01DTbwZ0E4MiL7sFd83lfoPiO2qMErDIE0LKg1b6vS8fobxdSxCMWq/vHL 3iS6ogEOimjCmUuu3F7UuzVCdJY8A9YKlGK94kqB82yfdIkW4BZcxQPUF7xLU04R Wq+jvV5PfjREEQdqGpNmjmfYVjgocdgLjxgAa40bZvVDKMTH0UMC1QN6VFRJWLHI LKLBXjSRGEI56csrHu7fcztN7l2YZeru/gzWy9ZgRnAea19SEps6r+BC0dhBAiSL qPmVSk45PKlEjYoQ9o7Co9bI7tS0My0Sj885WAltBSyqMX8wvpEvdiUeU2YisaD2 Yvv4h6J9SAXMI0doxnL9EvzqXbZYLoa7W+ZZP6sacKPC20Ou03JEAIqnlWSykkcc gxLosyhDfOmlP2Aeeu0Lsx7QB+CzmkwrT2burcatSY40hDgDvflRfN0GTZPetsOm 3sIPQ78wRp7dlznzbEez =C1aE -----END PGP SIGNATURE----- Changes: intel-microcode (3.20151106.1) unstable; urgency=medium * New upstream microcode data file 20151106 + New Microcodes: sig 0x000306f4, pf mask 0x80, 2015-07-17, rev 0x0009, size 14336 sig 0x00040671, pf mask 0x22, 2015-08-03, rev 0x0013, size 11264 + Updated Microcodes: sig 0x000306a9, pf mask 0x12, 2015-02-26, rev 0x001c, size 12288 sig 0x000306c3, pf mask 0x32, 2015-08-13, rev 0x001e, size 21504 sig 0x000306d4, pf mask 0xc0, 2015-09-11, rev 0x0022, size 16384 sig 0x000306f2, pf mask 0x6f, 2015-08-10, rev 0x0036, size 30720 sig 0x00040651, pf mask 0x72, 2015-08-13, rev 0x001d, size 20480 * This massive Haswell + Broadwell (and related Xeons) update fixes several critical errata, including the high-hitting BDD86/BDM101/ HSM153(?) which triggers an MCE and locks the processor core (LP: #1509764) * Might fix critical errata BDD51, BDM53 (TSX-related) * source: remove superseded upstream data file: 20150121 * Add support for supplementary microcode bundles: + README.source: update and mention supplementary microcode + Makefile: support supplementary microcode Add support for supplementary microcode bundles, which (unlike .fw microcode override files) can be superseded by a higher revision microcode from the latest regular microcode bundle. Also, fix the "oldies" target to have its own exclude filter (IUC_OLDIES_EXCLUDE) * Add support for x32 arch: + README.source: mention x32 + control,rules: enable building on x32 arch (Closes: #777356) * ucode-blacklist: add Broadwell and Haswell-E signatures Add a missing signature for Haswell Refresh (Haswell-E) to the "must be updated only by the early microcode update driver" list. There is at least one report of one of the Broadwell microcode updates disabling TSX-NI, so add them as well just in case -- Henrique de Moraes Holschuh <[email protected]> Mon, 09 Nov 2015 23:07:32 -0200
